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full/low speed usb digital isolator ADUM3160 rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2010 analog devices, inc. all rights reserved. features usb 2.0 compatible enhanced system-level esd performance per iec 61000-4-x 4.0 v to 5.5 v operation 7 ma maximum upstream supply current at 1.5 mbps 8 ma maximum upstream supply current at 12 mbps 2.5 ma maximum upstream idle current bidirectional communication upstream short-circuit protection high temperature operation: 105c low and full speed data rate: 1.5 mbps and 12 mbps high common-mode transient immunity: >25 kv/s 16-lead soic wide body package safety and regulatory approvals ul recognition: 2500 v rms for 1 minute per ul 1577 csa component acceptance notice #5a iec 60950-1: 400 v rms (reinforced) vde certificate of conformity din v vde v 0884-10 (vde v 0884-10):2006-12 v iorm = 560 v peak applications usb peripheral isolation isolated usb hub repeaters general description the ADUM3160 1 is a usb port isolator, based on analog devices, inc., i coupler? technology. combining high speed cmos and monolithic air core transformer technology, this isolation component provides outstanding performance characteristics and is easily integrated with low and full speed usb-compatible peripheral devices. many microcontrollers implement usb so that it presents only the d+ and d? lines to external pins. this is desirable in many cases because it minimizes external components and simplifies the design; however, this presents particular challenges when isolation is required. because the usb lines must switch between actively driving d+/d? and allowing external resistors to set the state of the bus, the ADUM3160 provides mechanisms for detecting the direction of data flow and control over the state of the output buffers. data direction is determined on a packet-by-packet basis. the ADUM3160 uses the edge detection based i coupler technology in conjunction with internal logic to implement a transparent, easily configured, upstream-facing port isolator. isolating the upstream port provides several advantages in simplicity, power management, and robust operation. the isolator has propagation delay comparable to that of a standard hub and cable. it operates with the supply voltage on either side ranging from 3.0 v to 5.5 v, allowing connection directly to v busx by internally regulating the voltage to the signaling level. the ADUM3160 provides isolated control of the pull-up resistor to allow the peripheral to control connection timing. the device draws low enough idle current that a suspend state is not required. functional block diagram v bus2 gnd 2 v dd2 spd pin dd? dd+ gnd 2 16 15 14 13 12 11 10 9 reg pu logic reg pu logic v bus1 gnd 1 v dd1 pden spu ud? ud+ gnd 1 1 2 3 4 5 6 7 8 09125-001 figure 1. 1 protected by u.s. patents 5,952,849; 6, 873,065; 7,075,329. other patents pending.
ADUM3160 rev. 0 | page 2 of 12 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 general description ......................................................................... 1 functional block diagram .............................................................. 1 revision history ............................................................................... 2 specifications ..................................................................................... 3 electrical characteristics ............................................................. 3 package characteristics ............................................................... 4 regulatory information ............................................................... 4 insulation and safety-related specifications ............................ 4 din v vde v 0884-10 (vde v 0884-10) insulation characteristics .............................................................................. 5 recommended operating conditions ...................................... 5 absolute maximum ratings ............................................................6 esd caution...................................................................................6 pin configuration and function descriptions ..............................7 applications information .................................................................9 functional description .................................................................9 product usage ................................................................................9 power supply options ............................................................... 10 pc board layout ........................................................................ 10 dc correctness and magnetic field immunity ..................... 10 insulation lifetime ..................................................................... 11 outline dimensions ....................................................................... 12 ordering guide .......................................................................... 12 revision history 7/10revision 0: initial version
ADUM3160 rev. 0 | page 3 of 12 specifications electrical characteristics 4.0 v v bus1 5.5 v, 4.0 v v bus2 5.5 v; 3.0 v v dd1 3.6 v, 3.0 v v dd2 3.6 v. all minimum/maximum specifications apply over the entire recommended operation range, unless otherwise noted; all typical specifications are at t a = 25c, v dd1 = v dd2 = 3.3 v. all voltages are relative to their respective ground. table 1. parameter symbol min typ max unit test conditions dc specifications total supply current 1 1.5 mbps v dd1 or v bus1 supply current i dd1 (l) 5 7 ma 750 khz logic signal rate, c l = 450 pf v dd2 or v bus2 supply current i dd2 (l) 5 7 ma 750 khz logic signal rate, c l = 450 pf 12 mbps v dd1 or v bus1 supply current i dd1 (f) 6 8 ma 6 mhz logic signal rate, c l = 50 pf v dd2 or v bus2 supply current i dd2 (f) 6 8 ma 6 mhz logic signal rate, c l = 50 pf idle current v dd1 or v bus1 idle current i dd1 (i) 1.7 2.5 ma input currents i dd? , i dd+ , i ud+ , i ud? , i spd , i pin , i spu , i pden ?1 +0.1 +1 a 0 v v dd? , v dd+ , v ud+ ,v ud? , v spd , v pin , v spu , v pden 3.0 single-ended logic high input threshold v ih 2.0 v single-ended logic low input threshold v il 0.8 v single-ended input hysteresis v hst 0.4 0.7 v differential input sensitivity v di 0.2 v |v xd+ ? v xd? | differential common-mode voltage range v cm 0.8 2.5 v logic high output voltages v oh 2.8 3.6 v r l = 15 k, v l = 0 v logic low output voltages v ol 0 0.3 v r l = 1.5 k, v l = 3.6 v v dd1 and v dd2 supply under voltage lockout v uvlo 2.5 3.0 v v bus1 and v bus2 supply under voltage lockout v uvlob 3.6 4.3 v transceiver capacitance c in 10 pf ud+, ud?, dd+, dd? to ground capacitance matching 10 % full speed driver impedance z outh 4 20 impedance matching 10 % switching specifications, i/o pins, low speed data rate 2 1.5 mbps c l = 50 pf propagation delay 3 t phl , t plh 325 ns c l = 50 pf side 1 output rise/fall time (10% to 90%) low speed t rf , t ff 75 300 ns c l = 200 pf, spd = spu = low side 2 output rise/fall time (10% to 90%) low speed t rf , t ff 75 300 ns c l = 450 pf, spd = spu = low low speed differential jitternext transition |t ljn | 45 ns c l = 50 pf low speed differential jitterpaired transition |t ljp | 15 ns c l = 50 pf switching specifications, i/o pins, full speed maximum data rate 4 12 mbps c l = 50 pf propagation delay 5 t phl , t plh 20 60 750 ns c l = 50 pf output rise/fall time (10% to 90%) full speed t r , t fl 4 20 ns c l = 50 pf, spd = spu = high full speed differential jitternext transition |t hjn | 3 ns c l = 50 pf full speed differential jitterpaired transition |t hjp | 1 ns c l = 50 pf
ADUM3160 rev. 0 | page 4 of 12 parameter symbol min typ max unit test conditions common-mode transient immunity at logic high output 6 |cm h | 25 35 kv/s v ud+ , v ud? , v dd+ , v dd? = v dd1 or v dd2 , v cm = 1000 v, transient magnitude = 800 v common-mode transient immunity at logic low output 6 |cm l | 25 35 kv/s v ud+ , v ud? , v dd+ , v dd? = 0 v, v cm = 1000 v, transient magnitude = 800 v 1 the supply current values for the device ru nning at a fixed continuous data rate 50% duty cycle, alternat ing j and k states. s upply current values are specified with usb-compliant load present. 2 the maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed. 3 t phl propagation delay is measured from the 50% level of the falling edge of the v ix signal to the 50% level of the falling edge of the v ox signal. t plh propagation delay is measured from the 50% level of the rising edge of the v ix signal to the 50% level of the rising edge of the v ox signal. 4 the maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed. 5 t phl propagation delay is measured from the 50% level of the falling edge of the v ix signal to the 50% level of the falling edge of the v ox signal. t plh propagation delay is measured from the 50% level of the rising edge of the v ix signal to the 50% level of the rising edge of the v ox signal. 6 cm h is the maximum common-mode voltage slew rate that can be sustained while maintaining v o > 0.8 v dd2 . cm l is the maximum common-mod e voltage slew rate that can be sustained while maintaining v o < 0.8 v. the common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. the transient magnitude is the range over which the common mode is slewed. package characteristics table 2. parameter symbol min typ max unit test conditions resistance (input to output) 1 r i-o 10 12 capacitance (input to output) 1 c i-o 2.2 pf f = 1 mhz input capacitance 2 c i 4.0 pf ic junction-to-case thermal resistance, side 1 jci 33 c/w thermocouple located at center of package underside ic junction-to-case thermal resistance, side 2 jco 28 c/w 1 the device is considered a 2-terminal device; pin 1, pin 2, pin 3, pin 4, pin 5, pin 6, pin 7, and pin 8 are shorted together and pin 9, pin 10, pin 11, pin 12, pin 13, pin 14, pin 15, and pin 16 are shorted together. 2 input capacitance is from any input data pin to ground. regulatory information the ADUM3160 has been approved by the organizations listed in table 3 . see table 10 and the insulation lifetime section for details regarding recommended maximum working voltages for spec ific cross-isolation wavefo rms and insulation levels. table 3. ul csa vde recognized under 1577 component recognition program 1 approved under csa component acceptance notice #5a certified according to din v vde v 0884-10 (vde v 0884-10):2006-12 2 single protection 2500 v rms isolation voltage basic insulation per csa 60950-1-07 and iec 60950-1 2 nd ed, 600 v rms (849 v peak) maximum working voltage 3 reinforced insulation, 560 v peak file e214100 file 205078 file 2471900-4880-0001 1 in accordance with ul 1577, each ADUM3160 is proof tested by applying an insulation test voltage 3000 v rms for 1 sec (curren t leakage detection limit = 5 a). 2 in accordance with din v vde v 0884-10, each ADUM3160 is proof tested by applying an insulation test voltage 1050 v peak for 1 sec (partial discharge detection limit = 5 pc). the * marking branded on the component indicates din v vde v 0884-10 approval. 3 see for recommended maximum working vo ltages under various operating conditions. table 8 insulation and safety-related specifications table 4. parameter symbol value unit conditions rated dielectric insulation voltage 2500 v 1 minute duration minimum external air gap (clearance) l(i01) 8.0 min mm measured from input termin als to output terminals, shortest distance through air minimum external tracking (creepage) l(i02) 7.7 min mm measured from input termin als to output terminals, shortest distance path along body minimum internal gap (internal clearance) 0.017 min mm insulation distance through insulation tracking resistance (comparative tracking index) cti >175 v din iec 112/vde 0303 part 1 isolation group iiia material group (din vde 0110, 1/89, table 1)
ADUM3160 rev. 0 | page 5 of 12 din v vde v 0884-10 (vde v 0884-10) insulation characteristics these isolators are suitable for reinforced electrical isolation only within the safety limit data. maintenance of the safety d ata is ensured by protective circuits. the * marking on packages denotes din v vde v 0884-10 approval. table 5. description conditions symbol characteristic unit installation classification per din vde 0110 for rated mains voltage 150 v rms i to iv for rated mains voltage 300 v rms i to iii for rated mains voltage 400 v rms i to ii climatic classification 40/105/21 pollution degree per din vde 0110, table 1 2 maximum working insulation voltage v iorm 560 v peak input-to-output test voltage, method b1 v iorm 1.875 = v pr , 100% production test, t m = 1 sec, partial discharge < 5 pc v pr 1050 v peak input-to-output test voltage, method a v iorm 1.6 = v pr , t m = 60 sec, partial discharge < 5 pc v pr after environmental tests subgroup 1 896 v peak after input and/or safety test subgroup 2 and subgroup 3 v iorm 1.2 = v pr , t m = 60 sec, partial discharge < 5 pc 672 v peak highest allowable overvoltage transient overvoltage, t tr = 10 seconds v tr 4000 v peak safety-limiting values maximum value allowed in the event of a failure (see figure 2 ) case temperature t s 150 c side 1 current i s1 265 ma side 2 current i s2 335 ma insulation resistance at t s v io = 500 v r s >10 9 case temperature (c) safety-limiting current (ma) 0 0 350 300 250 200 150 100 50 50 100 150 200 side 1 side 2 09125-002 figure 2. thermal derating curve, dependence of safety-limiting values with case temperature per din v vde v 0884-10 recommended operat ing conditions table 6. parameter symbol min max unit operating temperature t a ?40 +105 c supply voltages 1 v bus1 , v bus2 3.0 5.5 v input signal rise and fall times 1.0 ms 1 all voltages are relative to their respective ground. see the sectio n for information on immunity to external magnetic fields. dc correctness and magnetic field immunity
ADUM3160 rev. 0 | page 6 of 12 absolute maximum ratings ambient temperature = 25c, unless otherwise noted. table 7. parameter rating storage temperature (t st ) ?40c to +150c ambient operating temperature (t a ) ?40c to +105c supply voltages (v bus1 , v bus2 , v dd1 , v dd2 ) 1 , 2 ?0.5 v to +6.5 v input voltage (v ud+ ,v ud? , v spu ) 1 ?0.5 v to v dd1 + 0.5 v output voltage (v dd? , v dd+ , v spd , v pin ) 1 ?0.5 v to v dd2 + 0.5 v average output current per pin 3 side 1 (i o1 ) ?10 ma to +10 ma side 2 (i o2 ) ?10 ma to +10 ma common-mode transients 4 ?100 kv/s to +100 kv/s 1 all voltages are relative to their respective ground. 2 v dd1 , v dd2 , v bus1 , and v bus2 refer to the supply voltages on the input and output sides of a given channel, respectively. 3 see for maximum rated curre nt values for various temperatures. figure 2 4 refers to common-mode transients across the insulation barrier. common- mode transients exceeding the ab solute maximum ratings may cause latch-up or permanent damage. stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. esd caution table 8. maximum continuous working voltage 1 parameter max unit constraint ac voltage, bipolar waveform basic insulation 565 v peak 50-year minimum lifetime ac voltage, unipolar waveform basic insulation 849 v peak maximum approved working voltage per iec 60950-1 dc voltage basic insulation 849 v peak maximum approved working voltage per iec 60950-1 1 refers to continuous voltage magnitude imposed across the isol ation barrier. see the insulation lifetime section for more deta ils.
ADUM3160 rev. 0 | page 7 of 12 pin configuration and fu nction descriptions v bus1 1 gnd 1 * 2 v dd1 3 pden 4 v bus2 16 gnd 2 * 15 v dd2 14 spd 13 spu 5 pin 12 ud? 6 dd? 11 ud+ 7 dd+ 10 gnd 1 * 8 gnd 2 * 9 ADUM3160 top view (not to scale) *pin 2 and pin 8 are internally connected, and connecting both to gnd 1 is recommended. pin 9 and pin 15 are internally connected, and connecting both to gnd 2 is recommended. 09125-003 figure 3. pin configuration table 9. pin function descriptions pin no. mnemonic direction description 1 v bus1 power input power supply for side 1. where the isolator is powered by the usb bus voltage (4.5 v to 5.5 v), connect the v bus1 pin to the usb power bus. where the isolator is powered from a 3.3 v power supply, connect v bus1 to v dd1 and to the external 3.3 v powers. a bypass to gnd 1 is required. 2 gnd 1 return ground 1. ground reference for isolator side 1. 3 v dd1 power input power supply for side 1. where the isolator is powered by the usb bus voltage (4.5 v to 5.5 v), the v dd1 pin should be used for a bypass capacitor to gnd 1 ; no other connections should be made. where the isolator is powered from a 3.3 v power supply, connect v bus1 to v dd1 and to the external 3.3 v power supply. a bypass to gnd 1 is required. 4 pden i pull-down enable. this pin is read when exiting reset. this pin must be connected to v dd1 for standard operation. when connected to gnd 1 while exiting from reset, the downstream pull-down resistors are disconnected, allowing buffer impedance measurements. 5 spu i speed select upstream buffer. active high logic input. selects the full speed slew rate and timing and the logic conventions when spu is high (for 3.3 v logic, use v dd1 if the pin is to be pulled high). this input must be set high or low and must match pin 10. 6 ud? i/o upstream d?. 7 ud+ i/o upstream d+. 8 gnd 1 return ground 1. ground reference for isolator side 1. 9 gnd 2 return ground 2. ground reference for isolator side 2. 10 dd+ i/o downstream d+. 11 dd? i/o downstream d?. 12 pin i upstream pull-up enable. spd controls the power connection to the pull-up for the upstream port. it can be tied to v dd2 for operation on power-up or tied to an external control signal for an application requiring delayed enumeration. 13 spd i speed select downstream buffer. active high logic in put. selects the full speed slew rate and timing and the logic conventions when spu is high (for 3.3 v logic, use v dd2 if the pin is to be pulled high). this input must be set high or low and must match pin 7. 14 v dd2 power input power supply for side 2. where the isolator is powered by the usb bus voltage (4.5 v to 5.5 v), the v dd2 pin should be used for a bypass capacitor to gnd 2 ; no other connections should be made. where the isolator is powered from a 3.3 v power supply, connect v bus2 to v dd2 and to the external 3.0 v to 3.3 v power supply. a bypass to gnd 2 is required. 15 gnd 2 return ground 2. ground reference for isolator side 2. 16 v bus2 power input power supply for side 2. where the isolator is powered by the usb bus voltage (4.5 v to 5.5 v), connect v bus2 to the usb power bus. where the isolator is powered from a 3.3 v power supply, connect v bus2 to v dd2 and to the external 3.0 v to 3.3 v power supply. a bypass to gnd 2 is required.
ADUM3160 rev. 0 | page 8 of 12 table 10. truth table, control sign als, and power (positive logic) v spu input 1 v ud+ , v ud? state 1 v bus1 , v dd1 state v bus2 , v dd2 state v dd+ , v dd? state 1 v pin input 1 v spd input 1 description h active powered powered active h h input and output logic set for full speed logic convention and timing. l active powered powered active h l input and output logic set for low speed logic convention and timing. l active powered powered active h h spu and spd must be set to the same value. mixed speed and logic convention is not allowed. h active powered powered active h l spu and spd must be set to the same value. mixed speed and logic convention is not allowed. x z powered powered z l x upstream side 1 presents a disconnected state to the usb cable. x x unpowered powered z x x when power is not present on side 1, the side 2 data output drivers revert to high-z within 32 bit times. side 2 initializes in a high-z state. x z powered unpowered x x x when power is not present on the v dd2 , the upstream side disconnects the pull-up and disables the upstream drivers within 32 bit times. 1 h = logic high (3.3 v logic level supplied by external supply or the on-chip regulator), l = logic low, x = dont care, z = hi gh impedance output.
ADUM3160 rev. 0 | page 9 of 12 applications information functional description usb isolation in the d+/d? lines is challenging for several reasons. first, access to the output enable signals is normally required to control the transceiver. some level of intelligence must be built into the isolator to interpret the data stream and determine when to enable and disable its upstream and downstream output buffers. second, the signal must be faithfully reconstructed on the output side of the coupler while retaining precise timing and not passing transient states such as invalid se0 and se1 states. in addition, the part must meet the low power requirements of the suspend mode. the i coupler technology is based on edge detection and, therefore, lends itself well to the usb application. the flow of data through the device is accomplished by monitoring the inputs for activity and setting the direction for data transfer based on a transition from the idle state. after data directionality is established, data is transferred until either an end of packet (eop) or a sufficiently long idle state is encountered. at this point, the coupler disables its output buffers and monitors its inputs for the next activity. during the data transfers, the input side of the coupler holds its output buffers disabled. the output side enables its output buffers and disables edge detection from the input buffers. this allows the data to flow in one direction without wrapping back through the coupler causing the i coupler to latch. timing is based on the differential input signal transition. logic is included to eliminate any artifacts due to different input thresholds of the differential and single-ended buffers. the input state is trans- ferred across the isolation barrier as one of three valid states, j, k, or se0. the signal is reconstructed at the output side with a fixed time delay from the input side differential input. the requirement for low power suspend mode is addressed by making the idle state power consumption lower than the suspend limit of 2.5 ma. the i coupler has no suspend feature apart from a low idle current that meets the required level. the ADUM3160 is designed to interface with an upstream- facing low/full speed usb port by isolating the d+/d? lines. an upstream-facing port supports only one speed of operation; therefore, the speed-related parameters, j/k logic level, and d+/d? slew rate are set to match the speed of the upstream- facing peripheral port (see tabl e 10 ). a control line on the downstream side of the ADUM3160 activates the idle state pull-up resistor. this allows the downstream port to control when the upstream port attaches to the usb bus. the pin can be tied to the peripheral pull-up, a control line, or the peripheral power supply depending on when the initial bus connect is performed. product usage the ADUM3160 is designed to be integrated into a usb peripheral with an upstream-facing usb port as shown in figure 4 . the key design points are as follows: ? the usb host provides power for the upstream side of the ADUM3160 through the cable. ? the peripheral supply provides power to the downstream side of the ADUM3160. ? the isolator interfaces with the d+/d? lines of the peri- pheral controller; therefore, it behaves like a single port hub to the peripheral. ? peripheral devices have a fixed data rate that is set at design time. the ADUM3160 has configuration pins, spu and spd, that are set by the user to match this speed on the upstream and downstream sides of the coupler. ? usb enumeration begins when either the d+ or d?line is pulled high at the peripheral end of the usb cable. control of the timing of this event is provided by the pin input on the downstream side of the coupler. ? integrated pull-up and pull-down resistors are internal to the coupler. usb host ADUM3160 cpu peripher a l power supply v bus gnd bus d+ d? d+ 3.3v d? 09125-004 figure 4. typical ad um3160 application the ADUM3160 is transparent to standard usb traffic; therefore, minimal modifications are required to add isolation to a peripheral design. the isolator does add propagation delay to the signals equivalent to a hub and cable; therefore, isolated peripherals must be treated as if there were a built-in hub when determining the maximum number of hubs in a data chain. delayed application of the upstream pull-up is an option that can be used if required but, in many cases, pin can simply be tied high to immediately apply the pull-up when peripheral power is applied.
ADUM3160 rev. 0 | page 10 of 12 power supply options in most usb transceivers, 3.3 v is derived from the 5 v usb bus through an ldo regulator. the ADUM3160 includes an internal ldo regulator on each side to perform this function. it also allows the regulator to be bypassed if 3.3 v is available directly. this feature is especially useful in peripherals in which there may not be a 5 v power rail. two power input pins are present on each side, v busx and v ddx . if 5 v is available, it is connected to v busx , and the internal regulator makes 3.3 v to run the coupler. if 3.3 v is available, it can be provided to both v busx and v ddx . this disables the regulator and powers the coupler directly from the 3.3 v supply. figure 5 shows how a typical application is connected if the upstream side of the coupler is getting power directly from the usb bus and the downstream side is receiving 3.3 v from the peripheral power supply. pc board layout the ADUM3160 digital isolator requires no external interface circuitry for the logic interfaces. for full speed operation, the d+ and d? line on each side of the device requires a 24 1% series termination resistor. these resistors are not required for low speed applications. power supply bypassing is required at the input and output supply pins (see figure 5 ). install bypass capacitors between v busx and v ddx on each side of the chip. the capacitor value should have a minimum value of 0.1 f and low esr. the total lead length between both ends of the capacitor and the power supply pin should not exceed 10 mm. bypassing between pin 2 and pin 8 and between pin 9 and pin 15 should also be considered unless the ground pair on each package side is connected close to the package. all logic level signals are 3.3 v and should be referenced to the local v ddx pin or 3.3 v logic signals from an external source. v bus1 gnd 1 v dd1 pden spu ud? ud+ gnd 1 v bus2 gnd 2 v dd2 spd pin dd? dd+ gnd 2 ADUM3160 v bus1 = 5.0v inpu t v dd1 = 3.3v output v bus2 = 3.3v input v dd2 = 3.3v input 09125-005 figure 5. suggested printed circuit board layout example in applications involving high common-mode transients, care should be taken to ensure that board coupling across the isolation barrier is minimized. furthermore, the board layout should be designed such that any coupling that does occur equally affects all pins on a given component side. failure to ensure this could cause voltage differentials between pins to exceed the device absolute maximum ratings, thereby leading to latch-up or permanent damage. dc correctness and magnetic field immunity positive and negative logic transitions at the isolator input cause narrow (~1 ns) pulses to be sent to the decoder via the trans- former. the decoder is bistable and is, therefore, either set or reset by the pulses, indicating input logic transitions. in the absence of logic transitions at the input for more than ~1 s, periodic refresh pulses indicative of the correct input state are sent to ensure dc correctness at the output. if the decoder receives no internal pulses of more than about 5 s, the input side is assumed to be unpowered or nonfunctional, in which case the isolator output is forced to a default state by the watchdog timer circuit (see table 10 ). the limitation on the magnetic field immunity of the ADUM3160 is set by the condition in which induced voltage in the trans- formers receiving coil is sufficiently large to either falsely set or reset the decoder. the following analysis defines the conditions under which this may occur. the 3 v operating condition of the ADUM3160 is examined because it represents the most suscep- tible mode of operation. the pulses at the transformer output have an amplitude greater than 1.0 v. the decoder has a sensing threshold at about 0.5 v, thus establishing a 0.5 v margin in which induced voltages can be tolerated. the voltage induced across the receiving coil is given by v = ( ? d / d t ) r n 2 ; n = 1, 2, , n where: is magnetic flux density (gauss). n is the number of turns in the receiving coil. r n is the radius of the n th turn in the receiving coil (cm). given the geometry of the receiving coil in the ADUM3160 and an imposed requirement that the induced voltage be, at most, 50% of the 0.5 v margin at the decoder, a maximum allowable magnetic field is calculated as shown in figure 6 . magnetic field frequency (hz) maximum allowable magnetic flux density (kguass) 1k 0.001 100 100m 10 1 0.1 0.01 10k 100k 1m 10m 09125-006 figure 6. maximum allowable external magnetic flux density
ADUM3160 rev. 0 | page 11 of 12 for example, at a magnetic field frequency of 1 mhz, the maximum allowable magnetic field of 0.2 kgauss induces a voltage of 0.25 v at the receiving coil. this is about 50% of the sensing threshold and does not cause a faulty output transition. similarly, if such an event were to occur during a transmitted pulse (and was of the worst-case polarity), it would reduce the received pulse from >1.0 v to 0.75 vstill well above the 0.5 v sensing threshold of the decoder. the preceding magnetic flux density values correspond to specific current magnitudes at given distances from the ADUM3160 transformers. figure 7 expresses these allowable current magnitudes as a function of frequency for selected distances. as shown, the ADUM3160 is extremely immune and can be affected only by extremely large currents operated at high frequency very close to the component. for the 1 mhz example noted, a 0.5 ka current must be placed 5 mm away from the ADUM3160 to affect component operation. magnetic field frequency (hz) maximum allowable current (ka) 1000 100 10 1 0.1 0.01 1k 10k 100m 100k 1m 10m distance = 5mm distance = 1m distance = 100mm 09125-007 figure 7. maximum allowable current for various current-to-ADUM3160 spacings note that, at combinations of strong magnetic field and high frequency, any loops formed by printed circuit board traces may induce error voltages sufficiently large enough to trigger the thresholds of succeeding circuitry. care should be taken in the layout of such traces to avoid this possibility. insulation lifetime all insulation structures eventually break down when subjected to voltage stress over a sufficiently long period. the rate of insulation degradation is dependent on the characteristics of the voltage waveform applied across the insulation. in addition to the testing performed by the regulatory agencies, analog devices carries out an extensive set of evaluations to determine the lifetime of the insulation structure within the ADUM3160. analog devices performs accelerated life testing using voltage levels higher than the rated continuous working voltage. accel- eration factors for several operating conditions are determined. these factors allow calculation of the time to failure at the actual working voltage. the values shown in table 8 summarize the peak voltage for 50 years of service life for a bipolar ac operating condition and the maximum csa/vde approved working voltages. in many cases, the approved working voltage is higher than the 50-year service life voltage. operation at these high working voltages can lead to shortened insulation life in some cases. the insulation lifetime of the ADUM3160 depends on the voltage waveform type imposed across the isolation barrier. the i coupler insulation structure degrades at different rates depending on whether the waveform is bipolar ac, unipolar ac, or dc. figure 8 , figure 9 , and figure 10 illustrate these different isolation voltage waveforms. bipolar ac voltage is the most stringent environment. the goal of a 50-year operating lifetime under the ac bipolar condition determines the analog devices recommended maximum working voltage. in the case of unipolar ac or dc voltage, the stress on the insul- ation is significantly lower. this allows operation at higher working voltages while still achieving a 50-year service life. the working voltages listed in table 8 can be applied while main- taining the 50-year minimum lifetime, provided the voltage conforms to either the unipolar ac or dc voltage case. any cross- insulation voltage waveform that does not conform to figure 9 or figure 10 should be treated as a bipolar ac waveform, and its peak voltage should be limited to the 50-year lifetime voltage value listed in table 8 . note that the voltage shown in figure 8 and figure 9 is presented as sinusoidal for illustration purposes only. the sinusoidal depiction is meant to represent any voltage waveform varying between 0 and some limiting value. the limiting value can be positive or negative, but the voltage cannot cross 0 v. 0v rated peak voltage 09125-008 figure 8. bipolar ac waveform 0v rated peak voltage 09125-009 figure 9. unipolar ac waveform 0v rated peak voltage 09125-010 figure 10. dc waveform
ADUM3160 rev. 0 | page 12 of 12 controlling dimensions are in millimeters; inch dimensions (in parentheses) are rounded-off millimeter equivalents for reference only and are not appropriate for use in design. compliant to jedec standards ms-013- aa 032707-b 10.50 (0.4134) 10.10 (0.3976) outline dimensions 0.30 (0.0118) 0.10 (0.0039) 2.65 (0.1043) 2.35 (0.0925) 10.65 (0.4193) 10.00 (0.3937) 7.60 (0.2992) 7.40 (0.2913) 0 . 7 5 ( 0 . 0 2 9 5 ) 0 . 2 5 ( 0 . 0 0 9 8 ) 45 1.27 (0.0500) 0.40 (0.0157) c oplanarity 0.10 0.33 (0.0130) 0.20 (0.0079) 0.51 (0.0201) 0.31 (0.0122) seating plane 8 0 16 9 8 1 1.27 (0.0500) bsc figure 11. 16-lead standard small outline package [soic_w] wide body (rw-16) dimension shown in millimeters and (inches) ordering guide model 1 number of inputs, v dd1 side number of inputs, v dd2 side maximum full speed data rate (mbps) maximum full speed propagation delay, 5 v (ns) maximum full speed jitter (ns) temperature range package description package option ADUM3160brwz 2 2 12 70 3 ?40c to +105c 16-lead soic_w rw-16 ADUM3160brwz-rl 2 2 12 70 3 ?40c to +105c 16-lead soic_w rw-16 eval-adum4160ebz evaluation board 1 z = rohs compliant part. ?2010 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. d09125-0-7/10(0)

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